The present disclosure relates generally to the electrical, electronic and computer arts and, more particularly, to semiconductor chips including MOSFET and JFET structures.
The analog implementation of neural networks is beneficial for efficient, low-power operation of cognitive tasks such as pattern recognition and natural language processing. Noise and, in particular, 1/f noise is harmful to analog computation and practically poses a fundamental limit on the power and area efficiency benefits of analog circuits, including those used for neuromorphic computing. Analog-to-digital-to-analog (A/D/A) nodes to reset the noise levels have been used to address such noise issues. However, the overhead associated with this technique is significant and counters the area-efficiency of analog electronics.
Field-effect transistors include source, drain and gate structures. A biasing voltage applied across gate and source terminals allows the flow of charge carriers, namely electrons or holes, between source and drain. Flicker (1/f) noise is generally considered the dominant noise source in field-effect transistors. As transistor dimensions are shrunk to improve the array density, the flicker noise intensity increases, hence limiting the resulting signal-to-noise ratio.
Junction field-effect transistors (JFETs) are characterized by doped channel regions, p-n junctions on one or more sides of the channels, and ohmic contacts forming the source and drain regions. Metal oxide semiconductor field-effect transistors (MOSFETs) include gate electrodes that are electrically insulated from operatively associated semiconductor channels by thin layers of dielectric material. MOSFETs having n-doped source and drain regions employ electrons as the primary current carriers while those having p-doped source and drain regions use holes as primary current carriers. Vertical field-effect transistors (VFETs) have configurations wherein the current between the drain and source regions is substantially normal to the surface of the die. A vertical field-effect transistor may, for example, include a semiconductor pillar or fin having top and bottom (base might refer to a BJT) regions comprising source/drain regions, the portion of the pillar between the source/drain regions defining a channel region.